1. Field of the Invention
The present invention relates to a wireless receiving device and, more particularly, a wireless receiving device for use, for example, for a base station in a mobile communication system which realizes high-speed and large-capacity communication such as data communication.
2. Description of the Background Art
In a mobile communication system (e.g. PHS: Personal Handyphone System), communication is executed between a mobile terminal device (hereinafter referred to as a terminal) and a radio base device (hereinafter referred to as a base station) by using a predetermined modulation system, for example, a known π/4 shift QPSK (Quadrature Phase Shift Keying) system.
In particular, on a reception side of the mobile communication system, a received signal is demodulated by using a predetermined demodulation system corresponding to a predetermined modulation system adopted on a transmission side (see e.g. Japanese Patent Laying-Open No. 2003-158557).
FIG. 8 is a functional block diagram showing a structure of a conventional PHS wireless receiving device (e.g. base station) adopting the π/4 shift QPSK system.
With reference to FIG. 8, a transmission signal with a radio frequency (RF) from other wireless device not shown is received by an antenna 100 and applied to an RF reception circuit 102. RF reception circuit 102, which includes an amplifier and a frequency conversion circuit not shown, subjects a received signal to necessary analog processing such as amplification and frequency conversion to convert the signal into an analog reception signal with an intermediate frequency (IF). The analog reception signal with the intermediate frequency is thereafter converted into a digital reception signal with a predetermined sampling frequency by an analog/digital (A/D) converter 104.
The digital reception signal is further applied to a synchronizing signal processing unit 106. Synchronous processing unit 106 obtains a correlation value peak by the correlation method with respect to a synchronization estimation period with a predetermined signal length to estimate a position corresponding to the correlation value peak as a synchronous position. Information related to a synchronous position and digital data of a received signal are transferred to a demodulation and detection processing unit 108.
Demodulation and detection processing unit 108 demodulates a received signal with a length of the synchronization estimation period with respect to an obtained synchronous position as a basis and applies the result to an error determination unit 110.
Error determination unit 110 compares a demodulated received signal with a length of a synchronization estimation period and a reference signal held in advance in a main control unit 112 and determines whether they are coincident or not, that is, whether an error exists to notify main control unit 112 of the result.
When the determination by error determination unit 110 finds that the two signals are coincident to result in determining that there is no error, demodulation and detection processing unit 108 considers the synchronous position as a true synchronous position to demodulate the entire received signal (data of one slot) with respect to the synchronous position as a basis, so that the demodulation output is output as a bit output through error determination unit 110.
In this structure, timing of sampling of an analog reception signal by A/D converter 104 is determined according to an instruction from a clock control unit 114. In more detail, A/D converter 104 adjusts timing of an internal clock generated internally in response to a control signal from clock control unit 114. The unit further samples the analog reception signal at the timing of the internal clock.
Here, in the wireless receiving device, in order to precisely sample a symbol point to prevent generation of a reception error in a signal processing unit at a succeeding stage, over-sampling is executed of making a sampling frequency be higher than a symbol frequency (hereinafter also referred to as a symbol rate).
FIG. 9 is a signal space diagram (transition diagram) of the π/4 shift QPSK system. In FIG. 9, transitional symbol points are linked by straight lines. In the π/4 shift QPSK system having a relatively small number of modulation multiple-valued numbers, a distance between transitional symbol points is relatively longer than that of a modulation system having a large number of modulation multiple-valued numbers which will be described later. In a conventional mobile communication system adopting such π/4 shift QPSK system, commonly adopted as a sampling frequency is four times a symbol rate.
Here, in a conventional mobile communication system, when over-sampling is executed at four times the symbol rate, even if timing of a sampled symbol point deviates from original timing, the frequency of generation of a reception error at the time of signal processing is extremely low.
This is because in the π/4 shift QPSK system, as shown in FIG. 9, symbol points are relatively apart from each other on the IQ coordinate plane, so that even if timing of the symbol point slightly deviates, the symbol point is correctly recognized as an original symbol point to prevent a reception error from occurring in signal processing.
On the other hand, in recent mobile communication systems, higher-speed and larger-capacity data transmission is demanded such as in data communication than in conventional voice communication and therefore modulation systems have been developed having more multiple-valued numbers than those of the above-described π/4 shift QPSK system. Known as one example of multiple-valued modulation systems of this kind is the 16QAM (Quadrature Amplitude Modulation) system which has been already put into practical use in certain kind of data communication.
FIG. 10 shows a signal space diagram (transition diagram) of the 16QAM system. In the 16QAM system, a symbol point of a received signal corresponds to any of a total of 16 signal points as a whole of the coordinate plane which are arranged four each in lattice in each quadrant on the IQ coordinate plane. This enables transmission of 4-bit data indicative of any of 16 signals at once.
On other hand, in the 16QAM system, because a distance between symbol points are short to congest, when the system is adopted as a PHS modulation system, if timing of symbol point sampling is inappropriate, the symbol points might be erroneously recognized to generate a reception error in signal processing.
Under these circumstances, for preventing a reception error resulted from such a deviation of sampling timing as in a multiple-valued modulation system, effective is increasing a sampling frequency in A/D converter 104 of FIG. 8.
Increasing a sampling frequency, however, involves an increase in the amount of digital signal processing at synchronous processing unit 106 at the succeeding stage to require enormous time for processing. Also involved is an increase in power consumption required for signal processing.